具有同步化输出的分频器

Frequency divider with synchronized outputs

Abstract

本发明描述一种同步化分频器,其可在频率上对时钟信号进行划分且提供具有良好信号特性的差分输出信号。在一个示范性设计中,所述同步化分频器包括单端分频器及同步电路。所述单端分频器在频率上对所述时钟信号进行划分且提供第一及第二单端信号,所述第一及第二单端信号可为具有时序偏斜的互补信号。所述同步电路基于所述时钟信号对所述第一及第二单端信号进行重新取样且提供具有减小的时序偏斜的差分输出信号。在一个示范性设计中,所述同步电路包括第一及第二开关以及第一及第二反相器。所述第一开关及所述第一反相器形成对所述第一单端信号进行重新取样的第一取样与保持电路或第一锁存器。所述第二开关及所述第二反相器形成对所述第二单端信号进行重新取样的第二取样与保持电路或第二锁存器。
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

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Cited By (1)

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    CN-103973301-BMarch 29, 2017瑞昱半导体股份有限公司产生全差动信号的单端操作振荡装置与方法